FFFF000000060001001277AA000000000060000000001001210000001-7EFF6EB60Â4800480243A0Á-1‚0Â3400Â2‚43A22AFFFF0‚‚10‚‚2‚00010000003A000000010AE040840‚‚2‚43A22AAE0028E00042E243A20000200000AE600000000AE0,Subject: Re: Hardware Project From: david@uow.edu.au (David Wilson) Date: Mon, Nov 16, 1998 15Ç3@ Message-id: "ntt" writes: >It is hard to imagine any significant project being undertaken which would >really benefit from this. It is almost impossible to get hold of devices (eg >EPROM) that would fit into the memory space (and those you do get, you >probably wouldn't want to use). Using larger devices would be a waste >without making available the rest of the memory which means using some form >of bank switching. I had already discarded 2716/2732 and reached 2764/6264 sized chips. Bank selection is included (1/4 is used for the slot space, the remainder is banked 3 ways into the C800-CFFF space). >How generic is the PAL/GAL to be (since you're also adding a TTL device as >well)? Just a standard 20V10 or similar. >PLDs are becoming inexpensive and readily available. It would be easy enough >to produce a trivial PLD design which would decode everything (get rid of >the NAND gate), provide /CS lines and addressing for modern memory devices >(eg 128Kx8 --> 512Kx8) making the entire space available through the 2K >C800:CFFF window using an arbitrary location (eg C0[n+8]0) for the bank >switching. Decoding the slot ROM (Cnxx) could force a certain bank (such as >bank zero which would presumably always be there). The PLD could also >convert the R/W line to /OE and /WE lines for memory. Very similar to my GAL design. Rather than using up the limited C0[8+n]X space I am using CFFC-E to select banks 0..2 while bank 3 is forced when IOSEL is asserted. The reason for a GAL is that it is relatively small and I have access to a GAL burner. >To make all of this happen, you need /IOSEL, /IOSTRB & /DEVSEL for the 3 >memory spaces Got them. > you need the 8 data bus lines to latch a bank number > (if you wanna make it simple make this read only) No need as I use A0-A2 instead. > A7:0 can go straight through to the memory chips... > A10:8 need to be latched (and driven) if you want to > force Cnxx accesses to a certain bank I feed A10:8 straight to the EPROM - this uses 8x256 bytes for the slot ROM but does allow slot dependant code rather than having to write PIC. > you need to produce the high 8 address lines > (latched from the data bus/forced by /IOSEL) I am producing A11 & 12. > you need to produce at least one /CS line Yep. > you need to convert R/W into /OE and /WE Currently /WE = R/W* and the GAL inverts R/W* to form /OE. >If you were to produce some generic 'application-specific' logic parts you >might as well do it properly... Very interesting ideas. Thanks for the input. -- David Wilson School of IT & CS, Uni of Wollongong, Australia david@uow.edu.au 000400000010000000030ADB1AE2100050000000A000000020AE2000060000005C000000020ÁC310‚‚ÁFFFF0‚C00000 30ÂÁ ‚‚ÁA20‚‚ÁFFFF0‚900000 10ÂÁ ‚‚Á000700000018000000010‚20Â180‚Á0008000000970000000140,Geneva40,4030 10000900000015000000022‚FA22A2‚FA22A000A00000021000000022‚7FFFFFFF22A2‚7FFFFFFF22A000B00000005000000020Â000C0000001600000001AE01EB‚D72D0‚1000F000000280000000050 11AE890C0‚ÂÁÂÁ‚‚ÁÂ00130000005E00000000DA91F8CE1C1D1E1F7F1B024,-.¦¹°­­.FFFF0FFFF0