From - Tue Sep  9 22:38:09 1997
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From: pubpc1@library.ucla.edu
Newsgroups: comp.sys.apple2
Subject: Re: IIgs Zip accelerator SRAM speeds
Date: 8 Sep 1997 22:23:57 GMT
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smcgroga@gandalf.Advent.COM (Stephen McGrogan) wrote:
>Recently I bought a ZipGS for my son, David.
>He gratefully plugged it into his IIgs and it ran wonderfully.
>Windows popup rapidly and Hyperstudio runs smoothly.  Very nice!
>
>After a few experiments we discovered that the Zip only had 32KB of SRAM
>and a 28.4Mhz oscillator, which gives the IIgs a 7.11 mhz clock speed.
>An order to a parts supplier quickly brought 32KB more SRAM and a 32mhz
>oscillator, giving an 8 mhz clock.  After these changes the IIgs
>performed even better!

How fast are the SRAMs?  Chances are, if they are 70ns or faster, you
can bump it up to 9MHz or 10MHz with a 36mhz or 40mhz oscillator.

>So, of course, it is time to "push the envelope"!  (Remember that
>to EEs all things fall into two categories:  1) Things that are
>broken and need to be fixed.  2) Things that will shortly be
>broken once they are played with enough.)
>I notice that in the FAQ on the Zip, it is mentioned that faster
>operation of the Zip requires faster SRAMs.  The FAQ mentions 15ns
>SRAMs for 12-15mhz clock speeds.

The FAQ is wrong.  I tried to point this out to Nate several times
to no avail.  _Some_ people get the Zip working with 15ns SRAMs in
both TAG and DATA, but many (including myself) have discovered that
15ns in both sets of sockets will crash the board.  What many have
done is to put 15ns SRAMs in the TAG sockets and 45ns to 70ns chips
in the DATA sockets.  For reasons that someone more familiar with
engineering can explain (I just read it over and over again here
on csa2), the DATA chips' refresh needs to be slower than the TAG
chips'.  Personally, I have mine running with 15ns in TAG and 70ns
in DATA and it runs extremely stable at 13.75MHz.

>My question is, if 65ns SRAMs work at 7-8 mhz (28-32mhz oscillators),
>why do I need 15ns SRAMs to run at 12-15mhz (48-60mhz oscillator)?
>What is the actual relationship between the SRAM speed and the
>oscillator clock speed?  Does the SRAM have to deliver the data
>in some fraction of a cycle minus a fixed constant, which forces much
>faster SRAM speeds as the clock rate increases?
>At what point will the 65ns SRAMs fail to be fast enough?

The 65C816, according to Western Design Center (the manufacturer) is
a very memory intensive chip.  It needs RAM with a high refresh rate
relative to the speed the CPU itself runs at (The SuperCPU accelerator
for the Commodore, which uses the 65C816 clocked to 20MHz, must use
very fast memory for example).


>The FAQ also indicated that one of the interface chips needed
>replacement for higher clock speeds.  I bought the new chip, but,
>strangely, it has a slower response characteristic, according its
>specs, than the version that is already installed.
>I must be incorrect in my spec reading unless there is some other
>side effect of the swap that I'm not considering.
>
>Steve McGrogan
>smcgroga@advent.com

Steve, you are correct in your spec reading.  Again, the FAQ is in
error for many cases.  Some people claim that the part needs to be
replaced for >12MHz.  I have my Zip clocked at 13.75MHz and did not
need to replace it.  Someone else (Matt Portune?) posted that his
Zip would crash if it _did_ have the replaced part, but is stable
at 15MHz with the original parts.  It all depends on your particular
Zip.  Good luck.

You may want to see my HyperCard IIGS stack on how to upgrade the
Zip.  In my opinion, it is a better source for Zip upgrade than the
dated FAQ.  It can be found on ground (look for the link in the
apple2/upload/Jun97 directory for ZipUpgrade.SHK).

-Scott G.