Subject: Re: 3 wires acia communication on apple2
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From: Rubywand <rubywand@swbell.net>
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Date: Tue, 05 Oct 1999 23:15:22 -0500
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sfbong writes ...
> 
>  Hi all,
> 
>  I have build a small Single board computer out of 6502A and would like to
>  link it to my Apple II+ using  serial interface.  So I build two simple
>  ACIA boards using 6850, one attached to the SBC and one to my
>  Apple using slot #2.  I only use 3 wires for their communication namelt
>  TX, RX and Ground.
> 
>  The speed is 2400 B/S and both sides using Polling method.  My problem was
>  the first few bytes are always wrong when I sent a command to hex dump
>  the monitor ROM of the SBC from my Apple.
> 
>  I have a frequency counter, and I make sure the Freq at the TXclk and
> RXclk of the
> 6850 was 16 times of 2400Hz and the acia was set up to 1 start, 8Bits,
> 2Stops
> and divide by 16   i.e.
> 
> lda #03, sta aciacr, lda #%00010001, sta aciacr
> 
>  Was it due to the baud rate was too high?
>  Or the 6850 on the SBC must be interrupt driven?
>  Or I must add the rest of the RS232 wires cts, rts, dcd ....etc so it
> could work.
> 
>  Any idea on how I can solve my problems?
 ....

     Have never used a 6850 in a design; but, in general, this sort of IC
supplies a way to use it without depending upon interrupts. For example, when
receiving, you get a Rcv Buffer Full (or similar) signal on a pin which your
software can monitor.

     Given correct baud rate, one reason for getting bad data is that the
Sender and/or Receiver systems are not correctly initialized. For example, the
the Sender's output register should be cleared prior to beginning a
transmission. (It should, then, clear itself as each byte is loaded in to the
Send buffer.)  Similarly, you want the Receiver to begin with an empty input
register.

     Another thing to check is that settings for Data Bits, Parity, and Stop
Bits are the same for the Sender and Receiver. The standard is 8 Data Bits, No
Parity, 1 Stop Bit ("8N1").

     By the way, one place polling software can mess up is in failing to verify
the Not True condition. For example, you watch bit 7 of some I/O address for a
0 which signals Buffer Full. When you get a 0, you read the data and stick it
somewhere. If your input loop does not verify that bit 7 (Buffer Full) has gone
back to 1 (= not full) before looking for the 0 condition, you may, with some
ACIA IC's, read a 0 because the ACIA has not had time to reset the signal.

     I do not know whether the 6850 needs to be told to ignore status signals
like CTS or whether the corresponding line would need to be tied Hi (e.g. +5
through a 1k resistor) or Lo (e.g. to GND or possibly a negative voltage).  In
a similar vein, you may need to tie unused input pins Hi or Lo to avoid random
triggering. This information would be included in the 6850 data sheet.




Rubywand