Sector Edited for spelling subject errors and archives without the authors consent by Dr. Tom :0 --------------------------------------------------- Subject: Thinking out loud about the Transwarp IIe From: bobryan9@my-deja.com Newsgroups: comp.sys.apple2.programmer Date: Sat, 15 Jul 2000 22:16:05 GMT Organization: Deja.com - Before you buy. Lines: 134 Message-ID: <8kqnqs$r74$1@nnrp1.deja.com> NNTP-Posting-Host: 209.79.221.232 X-Article-Creation-Date: Sat Jul 15 22:16:05 2000 GMT X-Http-User-Agent: Mozilla/4.0 (compatible; MSIE 4.01; Windows 98) X-Http-Proxy: 1.1 x71.deja.com:80 (Squid/1.1.22) for client 209.79.221.232 X-MyDeja-Info: XMYDJUIDbobryan9 Here's some thoughts I had the other day. I had the laptop with me so I typed while I thought. I'm not even close to an expert (thats why I'm in college), so if I've got something wrong correct me please. Operation of the Transwarp: " The 6502 in the Apple II can address up to 64k. The Transwarp IIe does the following: 1)high speed 65c02. The Apple II's 6502 is no longer used. 2)High speed RAM. The Apple II's RAM is no longer used ** 3)Circuitry to determine what memory is being addressed by the 6502 (MMU) **The card will function at it's maximum speed when nothing is being stored in the TEXT, GRAPHICS, or C000-CFFF area. When these areas are accessed by the processor the DATA READ/WRITE is directed to the Apple II through the peripheral card connector. The chips on the accelerator determine which memory location is being addressed by the 65c02. These chips would replace the MMU when not accessing areas on the main Apple II board.. If the memory location falls within the video area, or the I/O area, the processor slows down and writes the memory to the Apple II (through the peripheral card connector), and then speeds back up and continues processing. Some problems with the theory: The Transwarp has extra memory on it (256k of FastRAM). Is this Bank Switched according to AE's memory switching scheme (like in the Ramworks?). If so, the card needs extra circuitry to see if a value higher than 4 is stored into $C073, and if it is, it sends that value to the Apple II aux slot (does Access to the aux slot switches usually stay on the Transwarp Board, since it has 256k itself??). The eighty column softswitches come into play here. With 256k, there is Main RAM and 3 auxillary pages on the Transwarp. When any of the softswitches have been accessed (ones that change access from Main RAM to Aux RAM) and a number larger than 4 has been stored in $C073, the card has to switch from reading from its fast RAM to motherboard RAM... Then there is the eighty column screen... When in 80 column mode any WRITEs to AUX RAM in the 80 column text area or Double High Resolution Graphics area, the card has to slow down... OR the card could just store the currently used memory page in it's RAM...I just opened a whole can of worms inside my head and the possibilites are growing... There'd be alot of keeping track of which memory is where, and where do you put a page that WAS in the TW fast RAM when you load in another page??.... Perhaps it will copy the entire page back into the AUX slot RAM??? Ok, how about this: The first 64k contains the Main RAM, ROM, etc. The second contains Auxillary memory. The third and 4th 64k blocks contain Bank switched RAM... The board would still have to copy pages in and out of the Fast RAM when accessing pages higher than 4. The ROM contains self test software, speed test software, the startup code (Transwarp materializes on your screen, beeps, if you press 0 it goes to self test, etc...). (Maybe) the code to determine if the Bank switched RAM being accessed is already in fast RAM, and if the correct page is not then there is code to copy that page into the FAST RAM on the Transwarp (It would also have to write the old page back to the Aux slot). That would slow down bank switching The ROM most likely copies the Apple II ROM into its RAM also.. The board is speeding along at 3.5 Mhz and suddenly it happens upon a WRITE instruction to CXXX. I've traced the 7M signal and it goes through an inverter to PAL TW5B-Q. I that this PAL controls the timing. For regular operation of the board, the PAL gets the 7Mhz input and outputs a 3.5Mhz signal (divide by 2)... When a 'slow address' is accessed, the PAL would take the 7Mhz input, (divide by 7) and send the 1Mhz to the CPU. There is a switch on the board elsewhere to put the address and the DATA on the peripheral connector instead of the onboard RAM. If this is so, a new PAL needs to be developed if we'd like to speed up the Transwarp. If my theory is correct and we boost the speed to 14 MHz then the PAL would have to divide by 14 for slow RAM access. Or perhaps we could put a circuit between (the timing input to the 65c02) and (the transwarp board). When 1Mhz is detected, the signal is allowed to pass through to the processor. When 3.5 Mhz is detected, a faster signal is sent to the processor. I just closed one of the cans o' worms. The advertisement states the the Transwarp does NOT use cacheing. It does say that it accelerates Main RAM, Aux RAM, and ROM... It makes sense that the TW'GS uses Caching. RAM was REALLY expensive when the TWGS board was developed, so one small chunk of code was loaded to the board at a time. The IIe can only address 64k, so caching isn't needed. I still have no idea how Aux memory is handled. ROM is easily speeded up by copying it to the Transwarp on startup. Main RAM is easy too. Aux RAM would be easy if ALL of it was stored on the card. I don't understand how more RAM in the Aux slot could be speeded up easily. " I'm sure CIE 20 will help me out this semester and I'll understand more of it. It would be neat to make a Transwarp copy, with a megabyte or more onboard, faster processor. Another thing just came to me as I post this... You can "slow down" access to the slots. You can access a slot at 3.5 Mhz. How does this work?? What is the top speed of the MMU on the IIe mainboard? If you access a slot at 3.5 Mhz, you are sending data through the BUS at 3.5 Mhz, correct? I thought the Apple II wouldn't let you do this. One last thing. Slowing down access to slot6 (disk II drive) will allow you to use the disk drive. The card won't access if accessed at 3.5 Mhz... How does this work? The DOS code is timing sensitive. It seems that the timing loop in DOS would have to be slowed too. Perhaps the processor slows down when the drive motor is turned ON, the DOS timing loops execute, the drive motor is turned off (the accelerator senses this) and the processor is sped back up. Anyway, comment all you like. Bob Sent via Deja.com http://www.deja.com/ Before you buy.